1. Field of the Invention
The present invention relates to the technical field of displaying, and more particularly to an array substrate, a manufacturing method for the same, and a display device.
2. Description of the Prior Art
In the manufacturing process for an array substrate of the Thin Film Transistor-Liquid Crystal Display (TFT-LCD), an important procedure for ensuring the production yield rate lies in preventing and controlling the occurrence of discharging of the static electricity.
An Advanced Super Dimension Switch (ADS) LCD is taken as an example. Advanced Super Dimension Switch may form a multi-dimensional electric field mainly by an electric field generated by a slit electrode edge and another electric field generated between a slit electrode layer and a plate electrode layer on a same plane, so that each of all oriented liquid crystal molecules between the slit electrodes in a liquid crystal box and just above the electrodes may render a rotation, and thus the operation efficiency of the liquid crystals is improved and the light transmission efficiency is increased. The ADS may improve the image quality of a TFT-LCD product, and has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push Mura free, and etc.
FIG. 1 illustrates a layout diagram for an array substrate of a conventional ADS LCD, and the array substrate comprises an even data shorting bar 170 formed by etching a gate metal layer and an odd data shorting bar 171 formed by etching a data metal layer. The even data shorting bar 170 is coupled to a data line in even columns on the array substrate by a via hole, and the odd data shorting bar 171 is directly coupled to a data line in odd columns on the array substrate. During the dry etching process for forming an active layer pattern of a TFT channel region on the array substrate, ions and free radicals for etching the active layer are bombarded, so that the data metal layer pattern carries electrostatic charges, the electrostatic charges aggregated at different positions on the data line are in different electric potentials, and the electrostatic charges on the odd data line may migrate and achieve a balance by the odd data shorting bar. When the balancing process of a large amount of electrostatic charges is implemented in a temporal magnitude of nanoseconds or microseconds, the electrostatic discharging is generated. A peak value of the electrostatic discharging may reach dozens of amperes, the instantaneous power is very large, and the generated energy of the electrostatic discharging electromagnetic pulses is significant enough to burn down the metal of the odd data shorting bar, which results in that a detecting signal cannot be loaded for the array substrate during the subsequent array testing process. Thus the detecting and repairing of the electric defects deteriorates. Furthermore, the intensity of the electric field generated on the gate insulation layer at the overlap between the data metal layer pattern and the gate metal layer pattern is stronger and stronger along with the continuous aggregation of the electrostatic charges on the data lines. When the intensity approaches a certain level, the strong electric field may break down a weak point of the gate insulation layer, and release the electrostatic charges of the data metal layer to the gate metal layer. As a result, the data metal layer and the gate metal layer may be short circuited, and such generated electrostatic discharging may significantly reduce the production yield rates of the array substrate.